In the manufacturing of integrated circuits, after the individual devices, such as the transistors, have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This connection process is generally called "metalization" and is performed using a number of different photolithographic and deposition techniques.
In one connection process, which is called a "dual damascene" technique, two channels of conductive materials, are positioned in vertically separated planes perpendicular to each other and interconnected by a vertical "via" at their closest point.
The first channel part of the dual damascene process starts with the placement of a first channel dielectric layer, which would be fluorinated material with a low dielectric constant (Low K), over the semiconductor devices. A first damascene step photoresist is then placed over the dielectric layer and is photolithographically processed to form the pattern of the first channels. An anisotropic dielectric etch is then used to etch out the channel dielectric layer to form the first channel openings.
The damascene step photoresist is stripped and a thin adhesion/barrier layer is deposited to line the walls of the first channel opening. This adhesion/barrier layer acts as an adhesion/barrier to prevent diffusion of subsequently deposited conductive material into the dielectric layer and the semiconductor devices. It also ensures good adhesion and electrical contact of subsequent layers to the underlying semiconductor devices while improving the formation of subsequently deposited conductive material.
A seed layer is then deposited on the adhesion/barrier layer to act as the "seed" of conductive material for subsequent deposition of the channel conductive material. A first conductive material is then deposited on the seed layer to fill the channels and vias. The adhesion/barrier layer, the seed layer, and the conductive material are subjected to a chemical-mechanical polishing process which removes the layers and material above the first channel dielectric layer and damascenes the first conductive material in the first channel openings to form the first channels.
The via formation step of the dual damascene process starts with the deposition of a thin stop nitride over the first channels and the first channel dielectric layer. Subsequently, a separating dielectric layer is deposited on the stop nitride. This is followed by deposition of a thin via nitride. Then a via step photoresist is used in a photolithographic process to designate round via areas over the first channels.
A nitride etch is then used to etch out the round via areas in the via nitride. The via step photoresist is then removed, or stripped. A second channel dielectric layer, which is typically an dielectric layer, is then deposited over the via nitride and the exposed dielectric in the via area of the via nitride. A second damascene step photoresist is placed over the second channel dielectric layer and is photolithographically processed to form the pattern of the second channels. An anisotropic dielectric etch is then used to etch the second channel dielectric layer to form the second channel openings and, during the same etching process to etch the via areas down to the thin stop nitride layer above the first channels to form the vias. The damascene photoresist is then removed, and a nitride etch process removes the nitride above the first channels in the via areas. An adhesion/barrier layer is then deposited to line the vias and the second channel openings. This is followed by a deposition of the seed layer and then the second conductive material in the second channel openings and the vias to form the second channel and the via. A second chemical-mechanical polishing process leaves the two vertically separated, horizontally perpendicular channels connected by cylindrical vias.
The use of the dual damascene technique eliminates metal etch and dielectric gap fill steps typically used in the metalization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum to other metalization materials, such as copper, which are very difficult to etch.
One drawback of using copper is that copper diffuses rapidly through various materials. Unlike aluminum, copper also diffuses through dielectrics, such as oxides. When copper diffuses through dielectrics, it can cause damage to neighboring devices on the semiconductor. To prevent diffusion, materials such as tantalum (Ta), titanium (Ti), and tungsten (W), their alloys, or combinations thereof are used as adhesion/barrier materials for copper. Of these, tantalum is one of the preferred adhesion/barrier materials.
The problem with using tantalum is that it cannot be integrated with fluorinated low dielectric constant dielectric material since tantalum reacts with fluorine at temperatures about and above 250.degree. C. to form tantalum fluoride (TaF.sub.2). Since many processing operations take place above 400.degree. C., this means that tantalum can not be used with these dielectrics.
A solution, which would permit the use of a tantalum adhesion/barrier material with fluorinated dielectrics has been long sought, but has eluded those skilled in the art. As the semiconductor industry is moving from aluminum to copper and other type of materials with greater electrical conductivity and thinner channels and vias, it is becoming more pressing that a solution is found.